Method of manufacture an on-chip inductor having a square geometry and high Q factor

ABSTRACT

An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.

[0001] This patent application is claiming priority under 35 USC § 121to co-pending patent application entitled ON-CHIP INDUCTOR HAVING ASQUARE GEOMETRY AND HIGH Q FACTOR AND METHOD OF MANUFACTURE THEREOFhaving a serial number of 10/074,158 and a filing date of Feb. 12, 2002.

TECHNICAL FIELD OF THE INVENTION

[0002] This invention relates generally to integrated circuits and moreparticularly to on-chip inductors and on-chip transformers.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits (IC's) are known to include a substrate, oneor more dielectric layers on the substrate, and one or more metal layerssupported by a corresponding dielectric layer. The metal layers arefabricated in such a way to produce on-chip components such asresistors, transistors, capacitors, inductors, et cetera. How an on-chipcomponent is fabricated and the physical limits placed on on-chipcomponents are dictated by the technology used and foundry rulesgoverning such technology.

[0004] For example, CMOS technology is readily used for cost effectiveintegrated circuits. Foundries that manufacture CMOS integrated circuitsprovide rules governing the number of dielectric layers, number of metallayers, metal track sizes, spacing between metal tracks, angular bendsof metal tracks, and other aspects of integrated circuit production.

[0005] While CMOS technology and the corresponding foundry rules allowon-chip inductors to be created, the quality factor (i.e., the measureof a component's ability to produce a large output at a residentfrequency and selectivity of the component) is limited to a value of5-10. As is known, a circular trace pattern for an on-chip inductortheoretically has a greater Q factor than a square or rectangular tracepattern of similar inductance, but has a larger IC footprint andviolates foundry rules. As such, circular on-chip inductors are notused.

[0006] To emulate the benefits of a circular on-chip inductor, whilemaintaining compliance with foundry rules, many integrated circuitdesigners use an octagonal inductor. However, an octagonal inductor islarger than a similar trace length square or rectangular inductor. Assuch, IC designers choose between larger octagonal inductors with ahigher Q factor and smaller square or rectangular inductors with a lowerQ factor. In some instances, an octagonal inductor is impractical due toits size and yet a square or rectangular on-chip inductor is impracticaldue to its low quality factor. And, in all instances, smaller on-chipinductors with similar performance characteristics are preferred overlarger on-chip inductors.

[0007] Therefore, a need exists for a high quality factor rectangularand/or square on-chip inductor.

SUMMARY OF THE INVENTION

[0008] These needs and others are substantially met by the on-chipinductor and/or on-chip transformer disclosed herein. Such an on-chipinductor includes a dielectric layer and a conductive winding on thedielectric layer. The conductive winding has a substantially squaregeometry and has at least its exterior corners geometrically shaped toreduce impedance of the conductive winding at a particular operatingfrequency. Since the quality factor of an on-chip inductor is inverselyproportional to the effective series impedance of the inductor at anoperating frequency, by reducing the effective series impedance, thequality factor is increased. In addition, the inductor has lowercapacitance values in comparison to substantially equal inductors thatdo not practice the present invention, thus allowing the inductor of thepresent invention to have a higher self-resonance.

[0009] Other embodiments of the on-chip inductor include providing ageometric shaping of the internal and external corners at approximately135° each. Alternatively, the interior angle of a corner may beapproximately 90° while the exterior of the corner may be approximately135°. Further variations of the geometric shaping have multiple angleson the interior angle and multiple angles on the exterior angle. Stillfurther embodiments of the on-chip inductor include having a spiralconfiguration for the conductive winding, having conductive windings onone or more dielectric layers operably coupled together via metalbridges, and/or including a secondary winding to produce an on-chiptransformer.

[0010] Such an on-chip conductor and/or on-chip transformer may bemanufactured by creating a dielectric layer and then creating aconductive winding on the dielectric layer. The conductive winding iscreated to have a substantially square geometry where its corners aregeometrically shaped to reduce impedance of the on-chip inductor at anoperating frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIGS. 1A and 1B illustrate an on-chip inductor in accordance withthe present invention;

[0012]FIGS. 2A and 2B illustrate an alternate embodiment of an on-chipinductor in accordance with the present invention;

[0013]FIGS. 3A and 3B illustrate another embodiment of an on-chipinductor in accordance with the present invention;

[0014]FIGS. 4A and 4B illustrate yet another embodiment of an on-chipinductor in accordance with the present invention;

[0015]FIGS. 5A and 5B illustrate a further embodiment of an on-chipinductor in accordance with the present invention;

[0016]FIGS. 6A and 6B illustrate yet a further embodiment of an on-chipinductor in accordance with the present invention;

[0017]FIGS. 7A, B and C illustrate an on-chip transformer in accordancewith the present invention;

[0018]FIG. 8 illustrates a logic diagram of a method for manufacturingan on-chip inductor in accordance with the present invention; and

[0019]FIG. 9 illustrates a logic diagram of a method for manufacturingan on-chip transformer in accordance with the present invention.

DETAIL DESCRIPTION OF A PREFERRED EMBODIMENT

[0020]FIGS. 1A and 1B illustrate an on-chip inductor 10 that includes awinding 12 on a dielectric layer 14. The winding 12 includes geometricshaping 16 at its exterior corners. As illustrated, winding 12 has asubstantially square shape and may include one or more turns on one ormore dielectric layers. By including the geometric shaping 16, theeffective impedance at operating frequencies (e.g., 2.4 gigahertz) isreduced, thereby increasing the quality factor of on-chip inductor 10.

[0021] In general, the inductance value of an on-chip inductor isdependent on the length of the interior edge of the metalization (i.e.,the interior edge of winding 12) where the current tends to concentrate.Accordingly, the interior diameter of the inductor is the decidingfactor for size minimization. As has been demonstrated in simulations,the highest current density is distributed on the interior edge of aninductor and gives the dominate contribution to the inductance. Notethat the simulations were performed at 1.6 gigahertz and 2.4 gigahertz.As such, the inductance of an on-chip inductor is increased byincreasing the length of its interior edge. This favors a rectangulardesign rather than an octagonal one, occupying the same rectangular areaon an integrated circuit and having the same track width.

[0022] To improve the quality factor of rectangular on-chip inductorsand/or square on-chip inductors, current turbulence within the metaltrack needs to be reduced. Such turbulence consumes power as resistiveloss, but does not contribute to the inductive value. Thus, byeliminating, or reducing current turbulence, by cutting the corners ofwinding 12, the resistive loss due to turbulence is reduced and theinductance value is not affected. As such, by including the 135° cornerson the exterior of the winding, as illustrated in FIGS. 1A and 1B, thecurrent turbulence is reduced, thus reducing resistive loss withouteffecting the inductance value. As is known, the quality factor for aninductor equals 2(pi)fL/R, where f is the operating frequency, L is theinductance, and R is the effective series resistance at the operatingfrequency. Thus, by maintaining the same inductance value and reducingthe effective impedance at the operating frequency, the quality factoris increased. In simulations, the quality factor has been improved by atleast 5% and in general is improved by at least 20%. As such, on-chipinductor 10 has the benefits over an octagonal inductor of similarinductance value in that it has a smaller integrated circuit footprint,can achieve similar inductance values and similar or greater qualityfactor values, and has lower capacitance values.

[0023]FIGS. 2A and 2B illustrate an on-chip inductor 20 that includeswinding 22 formed on dielectric layer 14. Winding 22 includes geometricshape 26 at each of its corners. Winding 22 may be one or more turns onone or more dielectric layers to produce the on-chip inductor 20.

[0024] The geometric shape 26 has the interior and exterior angles ofeach corner being approximately 135°. As such, the geometric shaping 26reduces the current turbulence within winding 22 and thus reduces theresistive loss without effecting the inductance value of on-chipinductor 20. As one of average skill in the art will appreciate, for theon-chip inductors of FIGS. 1 and 2, the geometric shaping 16 and 26 of135° at the corners, is well within the current foundry rules for CMOStechnology.

[0025]FIGS. 3A and 3B illustrate an on-chip inductor 30 that includeswinding 32 created on dielectric layer 14. Winding 32 includes geometricshaping 36. In this embodiment, the geometric shaping 36 has angles onthe interior and exterior corners of winding 32. The geometric shaping,more closely approximates an octagon but does not create an octagonalshape. In comparison with on-chip inductor 20, on-chip inductor 30 hasmore deeply cut corners at 135° angles.

[0026]FIGS. 4A and 4B illustrate an on-chip inductor 40 that includeswinding 42 created on dielectric layer 14. Winding 42 includes a spiralconfiguration that may be on one or more dielectric layers. As shown,each corner of winding 42 is geometrically shaped 36. In this example,the geometric shaping is similar to the geometric shaping of FIG. 1where the external corners have 135° angles while the interior anglesare 90°. As one of average skill in the art will appreciate, thegeometric shaping as illustrated in FIGS. 2A and 2B, and 3A and 3B mayalso be used with a spiral winding 42.

[0027]FIGS. 5A and 5B illustrate on-chip inductor 50 that includeswinding 52 and dielectric layer 14. Winding 52 may be a single turn on asingle dielectric layer, a spiral winding on a single dielectric layer,a single turn on multiple dielectric layers and/or multiple turns onmultiple dielectric layers.

[0028] As illustrated, winding 52 includes geometric shaping 56 on itsexterior angles. In this illustration, the geometric shaping 56 includesmultiple angles at the corners. The angles for the geometric shaping 56are dependent on allowable angle cuts per the foundry rules.

[0029]FIGS. 6A and 6B illustrate on-chip inductor 60 that includeswinding 62 and dielectric layer 14. Winding 62 may be a single turn ondielectric layer 14, multiple turns on dielectric layer 14, multiplesingle turns on multiple dielectric layers or multiple turns on multipledielectric layers.

[0030] As shown, each corner of winding 62 is geometrically shaped 66.In this illustration, the geometric shaping 66 includes multiple angleson both the interior corner and exterior corner of the corners ofwinding 62. Again, the angles for such multiple angles are dependent onallowable foundry rules.

[0031]FIGS. 7A, B and C illustrate an on-chip transformer 70 thatincludes a primary winding 72 on dielectric layer 14, a secondarywinding 74 on dielectric layer 78. The primary winding 72 at each of itscorners includes geometric shaping 76. The secondary winding 74 includesgeometric shaping 76 at each of its corners. The geometric shaping 76may include a single angular cut on each of its exterior corners (asshown in FIG. 1), singular angle cuts on each of its interior andexterior angles (as illustrated in FIG. 2 or 3), multiple cuts on itsexterior corners (as illustrated in FIG. 5), or multiple angular cuts onits exterior and interior angles (as illustrated in FIG. 6).

[0032] As one of average skill in the art will appreciate, each of theprimary and secondary windings may be a single turn on a single layer,multiple turns on a single layer, multiple single turns on multiplelayers, and/or multiple spiral turns on multiple layers.

[0033]FIG. 8 illustrates a logic diagram of a method for creating anon-chip inductor. The process begins at Step 80 where a dielectric layeris created on a substrate. The dielectric layer may be a silicondielectric, gallium arsenate, silicon germanium, and/or any othermaterial used to fabricate integrated circuits.

[0034] The process then proceeds to Step 82 where a conductive windingis created on the dielectric layer. The creation of the conductivewinding includes forming the winding to have a substantially squaregeometry and geometrically shaping its corners to reduce impedance ofthe on-chip inductor at an operating frequency. The geometric shapingmay be done as illustrated in FIGS. 1 through 3, 5, and 6. Thefabrication of the conductive winding may be done as illustrated inFIGS. 1 through 6.

[0035]FIG. 9 illustrates a logic diagram of a method for creating anon-chip inductor. The process begins at Step 90 where a primaryconductive winding that has a substantially square geometry is createdon a 1^(st) dielectric layer. The corners of the primary conductivewinding are geometrically shaped to reduce impedance of the primaryconductive winding at an operating frequency. The geometric shaping ofthe corners may be done as illustrated in FIGS. 1 through 3, 5, and 6.

[0036] The process then proceeds to Step 92 where a secondary conductivewinding that has a substantially square geometry is created on a 2^(nd)dielectric layer. The corners of the secondary conductive winding aregeometrically shaped to reduce impedance of the secondary conductivewinding at an operating frequency. The geometric shaping of the cornersmay be done as illustrated in FIGS. 1 through 3, 5 and 6. As one ofaverage skill in the art will appreciate, the creation of the primaryand secondary windings may be done by forming a single turn on a singledielectric layer, forming a single turn on multiple dielectric layers,forming multiple turns on a single dielectric layer or by formingmultiple turns on multiple dielectric layers.

[0037] The preceding discussion has presented an on-chip inductor thathas a substantially square geometry with an improved quality factor. Asone of average skill in the art will appreciate, other embodiments maybe derived from the teachings of the present invention, withoutdeviating from the scope of the claims.

What is claimed is:
 1. A method for manufacturing an on-chip inductorcomprises: creating a dielectric layer; and creating a conductivewinding on the dielectric layer, wherein the conductive winding has asubstantially square geometry, wherein corners of the conductive windingare geometrically shaped to reduce impedance of the on-chip inductor atan operating frequency.
 2. The method of claim 1, wherein the creatingof the conductive winding further comprises: creating the geometricshaping of the corners to include an interior angle per corner ofapproximately ninety degrees, and an exterior angle per corner ofapproximately one hundred thirty-five degrees.
 3. The method of claim 1,wherein the creating of the conductive winding further comprises:creating the geometric shaping of the corners to include an interiorangle per corner of approximately one hundred thirty-five degrees, andan exterior angle per corner of approximately one hundred thirty-fivedegrees.
 4. The method of claim 1 further comprises: creating theconductive winding to have a spiral configuration, wherein the cornersof the spiral configuration are geometrically shaped to reduce impedanceof the on-chip inductor at the operating frequency.
 5. The method ofclaim 1, wherein the creating of the conductive winding furthercomprises: creating a first winding on a first layer; creating a secondwinding on a second layer; and connecting the first winding to thesecond winding with at least one bridge.
 6. The method of claim 1,wherein the creating of the conductive winding further comprises:creating the geometric shaping of the corners to include angled exteriorcorners, wherein at least one angle per exterior corner reduces currentturbulence in the corner at the operating frequency.
 7. The on-chipinductor of claim 6, wherein the creating of the conductive windingfurther comprises: creating the geometric shaping of the corners toinclude angled interior corners, wherein at least one angle per interiorcorner further reduces current turbulence in the corner at the operatingfrequency.
 8. A method of manufacturing an on-chip transformercomprises: creating primary conductive winding that has a substantiallysquare geometry, wherein corners of the primary conductive winding aregeometrically shaped to reduce impedance of the primary conductivewinding at an operating frequency; and creating secondary conductivewinding that has a substantially square geometry, wherein corners of thesecondary conductive winding are geometrically shaped to reduceimpedance of the secondary conductive winding at an operating frequency,wherein the secondary conductive winding is magnetically coupled to theprimary conductive winding.
 9. The method of claim 8, wherein thecreating of the primary and secondary conductive windings furthercomprises: creating the geometric shaping of the corners to include aninterior angle per corner of approximately ninety degrees, and anexterior angle per corner of approximately one hundred thirty-fivedegrees.
 10. The method of claim 8, wherein the creating of the primaryand secondary conductive windings further comprises: creating thegeometric shaping of the corners to include an interior angle per cornerof approximately one hundred thirty-five degrees, and an exterior angleper corner of approximately one hundred thirty-five degrees.
 11. Themethod of claim 8 further comprises: creating dielectric layer; creatingthe primary conductive winding on the dielectric layer, wherein theprimary conductive winding includes a spiral configuration, wherein thecorners of the spiral configuration are geometrically shaped to reduceimpedance of the primary conductive winding at the operating frequency;and creating the secondary conductive winding on the dielectric layer,wherein the secondary conductive winding includes a secondary spiralconfiguration interwoven with the spiral configuration of the primaryconductive winding, wherein the corners of the secondary spiralconfiguration are geometrically shaped to reduce impedance of thesecondary conductive winding at the operating frequency.
 12. The methodof claim 8 further comprises: creating a first dielectric layer;creating the primary conductive winding on the first dielectric layer,wherein the primary conductive winding includes a spiral configuration,wherein the corners of the spiral configuration are geometrically shapedto reduce impedance of the primary conductive winding at the operatingfrequency; creating a second dielectric layer juxtaposed to the primaryconductive winding; and creating the secondary conductive winding on thesecondary dielectric layer, wherein the secondary conductive windingincludes the spiral configuration, wherein the corners of the spiralconfiguration are geometrically shaped to reduce impedance of thesecondary conductive winding at the operating frequency.
 13. The methodof claim 8, wherein creating each of the primary and secondaryconductive windings further comprises: creating a first winding on afirst layer; creating a second winding on a second layer; and connectingthe first winding to the second winding with at least one bridge. 14.The method of claim 8, wherein the creating of the primary and secondaryconductive windings further comprises: creating the geometric shaping ofthe corners to include angled exterior corners, wherein at least oneangle per exterior corner reduces current turbulence in the corner atthe operating frequency.
 15. The method of claim 14, wherein thecreating of the primary and secondary conductive windings furthercomprises: creating the geometric shaping of the corners to includeangled interior corners, wherein at least one angle per interior cornerfurther reduces current turbulence in the corner at the operatingfrequency.